(a) Field of the Invention
The present invention relates to a phase-change-type semiconductor memory device and, more particularly to a memory device having phase-change-type memory cells. The present invention also relates to a method for manufacturing the same.
(b) Description of the Related Art
Phase-change-type random-access-memory (PCRAM) devices are known wherein phase-change materials (chalcogenides) are used as memory elements. The PCRAM device has the advantages of a non-volatile storage function, a higher-speed operation and a higher capacity, and thus attracts a larger attention in these days. U.S. Pat. No. 6,531,373 describes a PCRAM device, which will be described hereinafter with reference to FIGS. 10A and 10B
In FIG. 10A, the PCRAM device 200 includes a plurality of bit lines BL (BL0 to BLn) extending in the row direction, a plurality of selection lines SL (SL1 to SLm) extending in the column direction, and a plurality memory cells, i.e., PCRAM cells 51 each disposed at a corresponding one of the intersections between the bit lines BL and selection lines SL. The PCRAM cells 51 each include a phase-change memory element, i.e., chalcogenide element 52 and a diode 53 having a p-n junction. The PCRAM cell 51 is connected between a corresponding one of the bit lines BL and a corresponding one of the selection lines SL such that the direction from the selection line SL to the bit line BL is the forward direction of the diode 53.
The chalcogenide element 52 is switched by a specific heat treatment from an amorphous state to a crystallized state, and vice versa. The chalcogenide element 52 stores information “1” or “0” corresponding to, for example, the amorphous state or crystallized state. The diode 53 is inserted therein for the purpose of preventing a so-called disturbance, i.e., preventing an unselected memory cell from being rewritten during rewriting of a selected memory cell, which is connected to the same bit line to which the unselected memory cell is connected. The diodes 53 may be replaced by selection switches such as MOSFETs.
To read data from the selected memory cell 51, a voltage is applied having a polarity such that the direction from a corresponding selection line SL to a corresponding bit line BL is the forward direction of the diode 53. Since the phase-change memory cell 52 generally has different electric resistances depending on the states thereof, the memory cell passes different currents depending on the states thereof during the voltage application. Thus, the data stored in the memory cell 51 can be identified by measurement of the current flowing through the memory cell 51 during the voltage application, after amplifying the current by using a sense amplifier (SA) 54.
As shown in FIG. 10B, on a semiconductor substrate 110 is formed a silicon layer with an intervention of an insulating film 120 therebetween to form a SOI (Silicon-on-Insulator) substrate 201. The area of the silicon layer is divided by a shallow trench isolation region 130 into a plurality of active regions 250. Each of the active regions 250 includes an n-type semiconductor region 150 and a p-type semiconductor region 160, which configure therebetween the p-n junction of the diode 53.
On the p-type semiconductor region 160 is formed a chalcogenide film 290 with an intervention of a contact region 260 therebetween. The selection lines 315 are formed on the chalcogenide film 290 with an intervention of barrier metal films 300 and 301. On the n-type semiconductor region 150 is formed a bit-line contact plug 350 with an intervention of a contact region 360 therebetween. The bit-line contact plug 350 is connected to the overlying bit line 140. A similar PCRAM device is also described in JP-A-5-21740.